Department of Linguistics and Intercultural Communication

We report on a 65 nm Ge pFET with a record performance of Ion = 478muA/mum and Ioff,s= 37nA/mum @Vdd= -1V. These improvements are quantified and understood with respect to halo/extension implants, minimizing series resistance and gate stack engineering. A better control of Ge in-diffusion using a low-temperature epi-silicon passivation process allows achieving 1nm EOT Ge-pFET with increased performance.

Physical and electrical characterization of a Dow Corning silsesquioxane-based ultra-low k dielectric is presented. The film properties, such as refractive index, SiH bond density, thermal stability and susceptibility to moisture absorption are investigated as a function of processing conditions. It is shown that exposure of the films to plasma environments results in a change of porosity. A low-K dielectric film with a pore size around 3.5 nm is successfully integrated in 0.2 μm single damascene structures

This work presents a process to fabricate FinFETs in bulk silicon with advancements in critical fabrication steps such as STI trench oxide recess and adjustment of fin height. These steps are accomplished with the adoption of Siconi™ Selective Material Removal (SMR™) in the fabrication flow. FinFETs obtained with this new integration scheme were tested in a co-fabrication process flow proposed to integrate planar CMOS and FinFETs in the same wafer. Morphological and electrical results indicate perfectly filled trenches, better fin height control and bulk FinFET static performance similar to planar CMOS.